Hitherto, to connect a semiconductor chip to a substrate, a wire bonding method using metal thin lines such as gold wires is widely used. To meet requirements for higher functions, larger scale integration, higher speed, and the like of semiconductor devices, a flip chip connection method (FC connection method) has been becoming popular, in which a conductive projection called a bump is formed on a semiconductor chip or a substrate to directly connect the semiconductor chip to the substrate.
As the flip chip connection method, there are known a method of performing metal bonding by using solder, tin, gold, silver, copper, and the like, a method of performing metal bonding by applying ultrasonic vibration, a method of maintaining mechanical contact by contractive force of a resin, and the like, and from the viewpoint of reliability of a connection portion, a method of performing metal bonding by using solder, tin, gold, silver, copper, and the like is generally used.
Examples of the flip chip connection method in connection between the semiconductor chip and the substrate also include a chip on board (COB) connection method frequently used in ball grid array (BGA), a chip size package (CSP), and the like. The flip chip connection method is also widely used in a chip on chip (COC) connection method in which bumps or circuits are formed on semiconductor chips to connect the semiconductor chips (for example, see Patent Literature 1).
In area-array semiconductor packages used in a CPU, an MPU, and the like, higher functions are strongly demanded. Specific examples of demands include an increase in size of chips, an increase in the number of pins (bumps or circuits), higher density of pitches and gaps.
In packages strongly required for a further reduction in size and thickness as well as higher functions, chip-stack package including chips layered and multi-staged by the above-described connection method, package on package (POP), through-silicon via (TSV), and the like are also spreading widely. Since such layering and multi-staging techniques dispose semiconductor chips in a stereoscopic manner instead of in a planar manner so that a smaller package can be attained, these techniques are effective in an improvement in performance of semiconductors and a reduction in noise, a packaging area, and energy consumption, and receive attention as a semiconductor wiring technique of the next generation.
From the viewpoint of an improvement in productivity, attention also has been paid to a chip on wafer (COW) in which a semiconductor chip is press-bonded (connected) onto a wafer and then singulated to thereby manufacture a semiconductor package and a wafer on wafer (WOW) in which wafers are press-bonded (connected) to each other and then singulated to thereby manufacture a semiconductor package. Furthermore, from the same point of view, attention also has been paid to a gang bonding method in which a plurality of chips are aligned on a wafer or a map substrate and temporarily press-bonded and the plurality of chips are mainly press-bonded collectively to secure connection. The gang bonding method is also used in the aforementioned TSV package (TSV-PKG) and the like.